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5962-0623501QPC, 5962-0623502QPC
Data Sheet March 29, 2007 FN6472.0
500MHz Rail-to-Rail Amplifiers
The 5962-0623501QPC, 5962-0623502QPC are fully DSCC SMD compliant parts and the SMD data sheets are available on the DSCC website (http://www.dscc.dla.mil/programs/specfind/default.asp). The 5962-0623501QPC is electrically equivalent to the EL8102 and the 5962-0623502QPC is electrically equivalent to the EL8103, reference these data sheets for additional information. These parts are single rail-to-rail amplifiers with a -3dB bandwidth of 500MHz and slew rate of 600V/s. Running off a very low 11mA supply current, the 5962-0623501QPC, 5962-0623502QPC also feature inputs that go to 0.15V below the VS- rail. The 5962-0623501QPC includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the 5962-0623501QPC is ideal for multiplexing applications. The 5962-0623501QPC, 5962-0623502QPC are designed for a number of general purpose video, communication, instrumentation, and industrial applications. Both parts are available in 8 Ld SBDIP. All are specified for operation over the -55C to +125C temperature range.
Features
* 500MHz -3dB bandwidth * 600V/s slew rate * Low supply current = 11mA * Supplies from 3V to 5.0V * Rail-to-rail output * Input to 0.15V below VS* Fast 25ns disable (5962-0623501QPC only)
Applications
* Video amplifiers * Portable/hand-held products * Communications devices
Pinouts
5962-0623501QPC (8 LD SBDIP) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 8 ENABLE 7 VS+ 6 OUT 5 NC
Ordering Information
PART NUMBER PART TEMP. PKG. MARKING RANGE (C) PACKAGE DWG. #
+
5962-0623501QPC 5962-0623 -55 to +125 8 Ld SBDIP D8.3 501QPC 5962-0623502QPC 5962-0623 -55 to +125 8 Ld SBDIP D8.3 502QPC
5962-0623502QPC (8 LD SBDIP) TOP VIEW
NC 1 IN- 2 IN+ 3 VS- 4 +
8 NC 7 VS+ 6 OUT 5 NC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
5962-0623501QPC, 5962-0623502QPC
Absolute Maximum Ratings (TA = +25C)
Supply Voltage from VS+ to VS-. . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Thermal Information
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60.5mW Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . .-55C to +125C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER INPUT CHARACTERISTICS RIN CIN Input Resistance Input Capacitance
VS+ = 5V, VS- = GND, TA = +25C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
Common Mode
3.5 0.5
M pF
OUTPUT CHARACTERISTICS ROUT Output Resistance AV = +1 30 m
ENABLE (5962-0623501QPC ONLY) tEN tDS Enable Time Disable Time 200 25 ns ns
AC PERFORMANCE BW -3dB Bandwidth AV = +1, RF = 0, CL = 5pF AV = -1, RF = 1k, CL = 5pF AV = +2, RF = 1k, CL = 5pF AV = +10, RF = 1k, CL = 5pF BW Peak GBWP PM SR tR tF OS tPD tS dG dP eN iN+ iN0.1dB Bandwidth Peaking Gain Bandwidth Product Phase Margin Slew Rate Rise Time Fall Time Overshoot Propagation Delay 0.1% Settling Time Differential Gain Differential Phase Input Noise Voltage Positive Input Noise Current Negative Input Noise Current RL = 1k, CL = 5pF AV = 2, RL = 100, VOUT = 0.5V to 4.5V 2.5VSTEP, 20% to 80% 2.5VSTEP, 20% to 80% 200mV step 200mV step 200mV step AV = +2, RF = 1k, RL = 150 AV = +2, RF = 1k, RL = 150 f = 10kHz f = 10kHz f = 10kHz AV = +1, RF = 0, CL = 5pF AV = +1, RL = 1k, CL = 5pF 500 140 165 18 35 1 200 55 600 4 2 10 1 15 0.01 0.01 12 1.7 1.3 MHz MHz MHz MHz MHz dB MHz V/s ns ns % ns ns % nV/Hz pA/Hz pA/Hz
2
FN6472.0 March 29, 2007
5962-0623501QPC, 5962-0623502QPC Pin Descriptions
PART 5962-0623501QPC 1, 5 2 3 4 6 7 8 5962-0623502QPC 1, 5, 8 2 3 4 6 7 PIN NAME NC ININ+ VSOUT VS+ ENABLE Not connected Inverting input Non-inverting input Negative power supply Amplifier output Positive power supply Enable and disable input FUNCTION
Simplified Schematic Diagram
VS+ I1 I2 R6 R7 R8
Q5 R3 R1 Q1 Q2 R2 IN-
Q6
VBIAS1
Q7
IN+
DIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR Q3 Q4 Q8 R4 R5 VS-
OUT
VBIAS2
R9
3
FN6472.0 March 29, 2007
5962-0623501QPC, 5962-0623502QPC Ceramic Dual-In-Line Metal Seal Packages (SBDIP)
c1 -A-DBASE METAL M -Bbbb S C A - B S BASE PLANE SEATING PLANE S1 b2 b AA D S2 -CQ A L DS b1 M (b) SECTION A-A (c) LEAD FINISH
D8.3 MIL-STD-1835 CDIP2-T8 (D-4, CONFIGURATION C)
8 LEAD CERAMIC DUAL-IN-LINE METAL SEAL PACKAGE INCHES SYMBOL A b b1 b2 b3 c c1 D E e eA eA/2 L Q S1 S2 MIN 0.014 0.014 0.045 0.023 0.008 0.008 0.220 MAX 0.200 0.026 0.023 0.065 0.045 0.018 0.015 0.405 0.310 MILLIMETERS MIN 0.36 0.36 1.14 0.58 0.20 0.20 5.59 MAX 5.08 0.66 0.58 1.65 1.14 0.46 0.38 10.29 7.87 2.54 BSC 7.62 BSC 3.81 BSC 3.18 0.38 0.13 0.13 90o 8 5.08 1.52 105o 0.38 0.76 0.25 0.038 NOTES 2 3 4 2 3 5 6 7 2 8 Rev. 0 4/94
E
eA e eA/2
c
0.100 BSC 0.300 BSC 0.150 BSC 0.125 0.015 0.005 0.005 90o 8 0.200 0.060 105o 0.015 0.030 0.010 0.0015
ccc M C A - B S D S
aaa M C A - B S D S
NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer's identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2. 5. Dimension Q shall be measured from the seating plane to the base plane. 6. Measure dimension S1 at all four corners. 7. Measure dimension S2 from the top of the ceramic body to the nearest metallization or lead. 8. N is the maximum number of terminal positions. 9. Braze fillets shall be concave. 10. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 11. Controlling dimension: INCH.
aaa bbb ccc M N
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 4
FN6472.0 March 29, 2007

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